1. Field of the Invention
The present invention relates to a semiconductor memory device and a method for manufacturing the same and more particularly, to a capacitor structure having high density in a dynamic random access memory (DRAM) array and a method for manufacturing the same.
2. Description of the Prior Art
Recently, significant progress has been made in a semiconductor memory device. For example, in a random access memory (RAM), various attempts to provide high integration density have been made without decreasing storage characteristics thereof.
FIG. 1 is a block diagram showing an example of a structure of a general RAM. Referring to FIG. 1, a plurality of word lines and a plurality of bit lines are arranged to intersect with each other in a memory cell array 1, a memory cell (not shown) being provided at each of intersections of the word lines and the bit lines. A particular memory cell is selected based on an intersection of a single word line selected by an X address buffer decoder 2 and a single bit line selected by a Y address buffer decoder 3. Data is written to the selected memory cell or data stored in the memory cell is read out. Write/read operation of the data is specified by a read/write control signal (R/W) applied to an R/W control circuit 4. At the time of writing data, input data (Din) is inputted to the selected memory cell through the R/W control circuit 4. On the other hand, at the time of reading out data, the data stored in the selected memory cell is detected and amplified by a sense amplifier 5 and outputted to the exterior through a data output buffer 6 as output data (Dout).
FIG. 2 is an equivalent circuit diagram of a dynamic memory cell shown for explaining write/read operation of a memory cell.
Referring to FIG. 2, each dynamic memory cell comprises a single field effect transistor 8 and a single capacitor 9. The field effect transistor 8 has one conduction terminal connected to one of the electrodes of the capacitor 9 and another conduction terminal connected to a bit line 7. In addition, the transistor 8 has a gate electrode connected to a word line 10. The capacitor 9 has other electrode connected to ground. At the time of writing data, since a predetermined potential is applied to the word line 10 so that the field effect transistor 8 is rendered conductive, charge from the bit line 7 is stored in the capacitor 9. On the other hand, at the time of reading out data, since a predetermined potential is applied to the word line 10 so that the field effect transistor 8 is rendered conductive, charge stored in the capacitor 9 is extracted through the bit line 7. As is obvious from the foregoing, storage capacity of a memory cell is based on the capacitance of its capacitor 9. Thus, in order to provide high integration of a memory cell array, various attempts to maintain and increase capacitance of each memory capacitor have been made. Such attempts are disclosed in, for example, Japanese Patent Publication Nos. 56266/1983 and 55258/1986 and Japanese Patent Laying-Open Gazette No. 65559/1985. As one kind of such attempts, a trench memory cell has been developed in which a trench is formed in a semiconductor substrate an a charge storage region is formed in the inner surface of the trench so that storage capacity can be maintained or increased.
FIG. 3 is a plan view of a dynamic RAM using such a trench memory cell, and FIG. 4 is a cross sectional view taken along a line A-A shown in FIG. 3. The trench memory cell is disclosed in, for example, an article by H. Sunami et al., entitled "A Corrugated Capacitor Cell", IEEE Trans. Electron Devices, Vol. ED-31, pp. 746-753.
Referring to FIGS. 3 and 4, a plurality of memory cells 12 are formed on the surface of a type silicon substrate 11. In FIG. 3, each of the memory cells 12 corresponds to a section formed by a dot and dash line. The adjacent memory cells 12 are isolated by an isolation field oxide film 13. A channel stop P.sup.+ region 14 for isolation is formed under the field oxide film 13. Each of the memory cells 12 comprises a charge storage region 15 for storing charges, an access transistor region 16 and an N.sup.+ region 18 connected to a bit line 17. More specifically, the charge storage region 15 comprises a trench 19 formed in the major surface of the P type silicon substrate 11, an N.sup.+ region 20 formed in a part of the major surface of the P type silicon substrate 11 including the inner surface of the trench 19 and serving as a memory terminal of a memory capacitor, a capacitor dielectric film 21 formed to cove the inner surface of the trench 19, and a cell plate electrode 22 formed on the capacitor dielectric film 21 and serving as an opposite electrode of the memory capacitor. In addition, the access transistor region 16 comprises N.sup.+ regions 18 and 20, a channel region 23 formed therebetween, and a word line 24 constituting a gate electrode. The bit line 17 is connected to the N.sup.+ region 18 through a contact hole 25.
Referring now to FIG. 4, description is made on write/read operation of data stored in the memory cell 12. At the time of writing data, since a predetermined potential is applied to the word line 24 so that an inversion layer is formed in the channel region 23, the N.sup.+ regions 18 and 20 are rendered conductive. Thus, charge from the bit line 17 is transferred to the charge storage region 15 through the channel region 23 and stored in the N.sup.+ region 20. On the other hand, at the time of reading out data, a predetermined potential is applied to the word line 24 so that the charge stored in the N.sup.+ region 20 is provided to the exterior through the inverted channel region 23, the N.sup.+ region 18 and the bit line 17.
The amount of charges thus stored depends on the area of the N.sup.+ region 20 formed in the inner surface of the trench 19, and formation of the trench 19 can contribute to formation of large charge storage capacitance while preventing increase of the planar area occupied by the charge storage region 15. More specifically, the trench 19 is formed and a trench capacitor using the trench 19 is used, so that a memory capacitor having a relatively large capacitance can be ensured while maintaining the area occupied by very fine memory cells.
However, the dynamic RAM shown in FIGS. 3 and 4 presents the following problems with respect to high integration density.
More specifically, in the conventional dynamic RAM, the P type silicon substrate 11 is set to be at a negative potential (about -3V). In addition, a potential of about 5V or about 0V is applied to the N.sup.+ region 20 (20a, 20b) serving as a charge storage region in response to memory information "1" or "0". Thus, a reverse bias voltage is usually applied between the N.sup.+ regions 20a and 20b and the P type silicon substrate 11 irrespective of the memory information. As a result, depletion regions 26a and 26b are formed around the N.sup.+ regions 20a and 20b. The higher the reverse bias voltage is or the lower the impurity concentration of the P type silicon substrate 11 is, the more easily the depletion regions 26a and 26b expand. Since the impurity concentration of the P type silicon substrate 11 is generally decreased with distance from the major surface, the depletion layers 26 a and 26b as represented by a dotted line in FIG. 4 expand. As a result, when it is desired to form the trenches 19a and 19b deep to increase storage capacity, the distance [the distance a represented by an arrow in FIG. 4) between the adjacent depletion regions 26a and 26b is further reduced. In addition, it is obvious that the distance is also reduced if the positions where the trenches 19a and 19b are formed are close to each other for high integration density. Thus, when the adjacent trenches 19a and 19b are close to each other and the trenches 19a and 19b are formed deeper for higher integration, a punch-through phenomenon finally occurs in which the depletion regions 26a and 26b come in contact with each other (a=0). When such a punch-through phenomenon occurs, conduction between adjacent memory cells occurs, so that charges stored in the N.sup.+ regions 20a and 20b interfere with each other due to the difference in memory information stored in the adjacent memory cells. As a result, the information holding characteristic is deteriorated. More specifically, it becomes difficult to decrease the spacing between the adjacent trenches 19a and 19b and form the trenches deeper, which presents a large difficulty in providing high integration of memory cells.
Additionally, in the dynamic RAM shown in FIGS. 3 and 4, a memory terminal of the memory capacitor comprises the N.sup.+ region 20 in the P type silicon substrate 11. Thus, carriers produced upon incidence of radioactive rays, such as alpha rays, into the silicon substrate flow into the N.sup.+ region 20 serving as a memory terminal of the memory capacitor, so that a malfunction (referred to as soft error hereinafter) occurs in which original memory information is inverted.